The present invention relates generally to a level translator circuit and more particularly to a level translator circuit for use between circuits having distinct power supplies.
Circuits for voltage level translation are utilized in a variety of applications. Level translator circuits are employed to allow circuits operating at different power supply potentials to communicate with one another. Typically, the area, power and performance of the translator circuit are critical to the operations of each of the different circuits.
FIG. 1 is a simple block diagram of a level translator system 10. The system 10 includes a level translator circuit 12 coupled between circuits 14 and 16. In this embodiment, Vddl circuit 14 is coupled to a lower voltage supply and Vddh circuit 16 is coupled to a higher voltage supply. Level translation is required only when a circuit on a lower voltage supply interfaces with one on a higher voltage supply. The level translates due to the voltage difference between Vddl circuit 14 and Vddh circuit 16, causing a resulting leakage current.
It is important that a level translator circuit operate efficiently, utilize minimal power, and translate from one voltage supply potential to another as quickly as possible. The speed and performance of conventional translator circuits are typically adversely affected by contention between transistors within the circuit during the translation. For a more detailed description of this issue, refer now to the following discussion in conjunction with the accompanying figures.
FIG. 2 illustrates a first embodiment of a conventional level translator circuit 100 coupled between distinct power supplies. In this circuit, cross-coupled pfet transistors 102 and 106 connected to the Vddh circuit 16xe2x80x2 are used in conjunction with pull-down nfet transistors 104 and nfet transistor 108 and an inverter 110 which is connected to the Vddl supply. The circuit 100 operates as follows: For propagation of a logical xe2x80x980xe2x80x99 from the Vddl circuit cloud 14xe2x80x2, transistor 104 is off, the inverter 110 produces a logical xe2x80x981xe2x80x99 at node-2 in the form of Vddl volts, which then turns on nfet transistor 108, driving node-Z to a logical xe2x80x980xe2x80x99, which in turn causes pfet transistor 102 to turn on, thereby raising node-1 to Vddh volts, which in turn causes pfet transistor 106 to turn off. Since the gate of pfet transistor 106 is at Vddh and the source of pfet transistor 106 is also at Vddh, there is no leakage. This circuit is non-inverting.
For propagation of a logical xe2x80x981xe2x80x99 from the Vddl circuit cloud 14xe2x80x2, nfet transistor 104 is on, resulting in node-1 being drawn toward a logical xe2x80x980xe2x80x99. The inverter 110 produces a logical xe2x80x980xe2x80x99 at node-2 in the form of 0 volts, which results in nfet transistor 108 turning off. Since node-1 is being drawn to 0 volts, pfet transistor 106 is now on, driving node-Z to a logical xe2x80x981xe2x80x99 in the form of Vddh volts, which in turn reinforces the node-1 potential of xe2x80x980xe2x80x99 by turning off pfet transistor 102.
FIG. 3 illustrates a second embodiment of a conventional level translator circuit 200 coupled between distinct power supplies. In this configuration, the inverter is eliminated and the source of nfet transistor 204 is connected to the gate input of the nfet transistor 208, which is connected to the output of the Vddl circuit 14xe2x80x3. Also, the gate of nfet transistor 204 is connected directly to the Vddl supply. This circuit 200 operates as follows: For propagation of a logical xe2x80x980xe2x80x99 from the Vddl circuit cloud 14xe2x80x3, nfet transistor 204 is on and nfet transistor 208 is off, thereby relinquishing control of node-Z. Since nfet transistor 204 is on, node-1 is now at O-volts turning on pfet transistor 206, raising node-Z to Vddh volts, which in turn shuts off pfet transistor 202, which reinforces the node-1 level of 0-volts. Also note that this circuit configuration is inverting.
For propagation of a logical xe2x80x981xe2x80x99 from the Vddl circuit, nfet transistor 204 is on until the voltage at node-1 can rise to Vddl-Vtn. This voltage rise begins to shut off pfet transistor 206. Nfet transistor 208 is now active and pulling node-Z low, which in turn activates pfet transistor 202, which raises the node-1 potential to Vddh, which in turn shuts off the leakage from pfet transistor 206.
In each of these embodiments, a basic problem is that there is a contention between nfet transistors 104 or 204 and pfet transistors 102 or 202 when translation takes place. When translation is initiated, these transistors are fighting each other for control of the output. In addition, due to sizing constraints, the nfet transistors 104 or 204 must be stronger than the pfet transistors 102 or 202. In so doing, there is poor rising low-to-high performance in the output node.
Accordingly, the contention between nfet transistors 104 or 204 and pfet transistors 102 or 202 affects the speed and performance of the level translator 100 or 200. Accordingly, what is desired is a level translator circuit that minimizes the time that these transistors are in contention so as to maximize the performance of the circuit and minimize its power dissipation. The circuit should be cost effective and have performance characteristics equal to or greater than conventional circuits. The circuits should also be easily implemented utilizing existing processes. The present invention addresses such a need.
A level translator circuit for use between a lower voltage potential circuit and a higher voltage potential circuit is disclosed. The translator circuit comprises a first transistor coupled to the lower voltage potential circuit and a bootstrap mechanism coupled to the first transistor. The circuit includes a second transistor coupled to the first transistor, a higher voltage potential and the higher voltage potential circuit, and a third transistor coupled to the higher voltage potential circuit, the higher voltage potential and the second transistor. Finally, the circuit includes a fourth transistor coupled to the higher voltage potential circuit, the third transistor and the lower voltage potential circuit. The bootstrap mechanism allows for the dynamic modulation of the first transistor to maximize translation speed and to minimize power consumption. A level translator circuit in accordance with the present invention utilizes a bootstrap mechanism in the gate of the input transistor to allow translating between a low voltage potential to a high voltage potential to be performed more efficiently.